1. Field of the Invention
This invention relates to semiconductor memory devices, and more particularly to MOS type semiconductor devices having a heavily doped impurity layer for inversion prevention formed in an element isolation region of a semiconductive substrate.
2. Description of the Related Art
With the increasing needs for high speed logic performance of digital systems, semiconductor memory devices formed with high integration density to have large capacity of memory space have received a great deal of attention. Typically, a semiconductor memory formed with high integration density has memory cells formed of metal-oxide semiconductor field effect transistors (MOSFETs). In order to enhance the integration density of the memory devices, the elements are formed in the finest permissible pattern. However, the this type of MOS type semiconductor devices presently available have various problems concerning the performance and reliability caused by micro-fabrication of the memory elements. Particularly, accomplishment of the compatibility of effective isolation between the elements and enhanced junction withstanding (breakdown) voltage may be one of the most important technical subjects which should be solved as soon as possible by the semiconductor manufacturers.
In the micro-fabrication of memory elements, effective isolation between the elements and enhanced junction withstanding voltage are dealt as conflict factors. As will be described hereinafter, it is not easy to accomplish the compatibility of effective isolation between the elements and enhanced junction withstanding (breakdown) voltage.
For example, in electrically erasable programmable read only memories, NAND type memory cells respectively connected to adjacent bit lines on a substrate are constructed by a series-connection of double gate type MOSFETs. Each of the NAND type memory cells is connected to a corresponding bit line via a selection transistor. A heavily-doped impurity layer is generally disposed as an element isolation layer between the adjacent selection transistors. The element isolation layer extends in parallel with the bit lines. A common gate electrode layer of the selection transistors is disposed insulatively above the substrate to intersect the bit lines.
With such an arrangement, in order to make the isolation by insulation between the elements more effective, it is required that the element isolation layer be formed on the substrate to project from the side end portion of the common gate electrode layer towards the contact portions of the bit lines. A distance between the side end portion of the common gate electrode layer and the terminal edge of the element isolation layer formed to project therefrom is selected with much care so as to prevent reduction in the field inversion voltage due to the roundabout of an electric field between the adjacent selection transistors. With the distance set larger, the roundabout of an electric field can be more effectively prevented and consequently the more effective element isolation can be attained.
However, increase in the projection distance of the element isolation layer leads to an undesired result of reduction in the junction withstanding voltage. This is because the active layers of the selection transistors and the element isolation layer may be made in electrical contact with each other when the projection end is set excessively near the contact portions of the bit lines. If the projection distance of the element isolation layer and the distance for the junction withstanding voltage are set to respective desired values at the same time, the integration density itself of the memory cell devices is lowered.